STAP16DPPS05 查看數據表（PDF） - STMicroelectronics
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STAP16DPPS05
STMicroelectronics
STAP16DPPS05 Datasheet PDF : 29 Pages
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STAP16DPPS05
VDD = 5 V, Tj = 25 °C, unless otherwise specified.
Electrical characteristics
Symbol
Table 8: Switching characteristics
(all table limits are guaranteed by design. Not tested in production.)
Parameter
Test condition
Min. Typ. Max. Unit
fclk
Clock frequency
CLK- OUTn ,
Cascade operation
VDD = 3.3 V
30 MHz
55 90
tPLH1
LE/DM1 = H,
OE/DM2 = L
VDD = 5 V
ns
30 50
tPLH2
LE/DM1- OUTn ,
OE/DM2 = L
VDD = 3.3 V
VDD = 5 V
48 80
ns
30 45
tPLH3
tPLH
OE/DM2 - OUTn ,
LE\\DM1 = H
CLK-SDO
tPHL1
tPHL2
CLK OUTn ,
LE/DM1 = H,
OE/DM2 = L
LE/DM1- OUTn ,
OE/DM2 = L
VIH = VDD
VIL = GND
IO = 20 mA
RL = 60 Ω
CL = 10 pF
VL = 3.0 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
70 120
ns
45 65
21 35
ns
15 25
28 35
ns
22 40
13 35
ns
12 18
tPHL3
tPHL
tON
tOFF
tr
tf
OE /DM2- OUTn ,
LE/DM1 = H
CLK-SDO
Output fall time
10~90 % of voltage
waveform
Output rise time
90~10 % of voltage
waveform
CLK rise time (1)
CLK fall time(1)
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
VDD = 3.3 V
VDD = 5 V
24 35
ns
21 30
24 40
ns
17 25
30 55
ns
10 20
4 10
ns
3
8
5
µs
5
Notes:
(1)If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.
DocID024306 Rev 7
7/29
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