STM32F051R4U7(2012) 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

STM32F051R4U7
(Rev.:2012)

Low- and medium-density advanced ARM™-based 32-bit MCU with 16 to 64 Kbytes Flash, timers, ADC, DAC and comm. interfaces

STMicroelectronics 

Electrical characteristics

STM32F051x

6.3.21

Communication interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Table 64 are derived from tests

performed under ambient temperature, fPCLK frequency and VDD supply voltage conditions

summarized in Table 20.

The I2C interface meets the requirements of the standard I2C communication protocol with

the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-

drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is

disabled, but is still present.

The I2C characteristics are described in Table 64. Refer also to Section 6.3.13: I/O port

characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

Table 64. I2C characteristics(1)

Symbol

Parameter

Standard mode

Min Max

Fast mode

Min

Max

Fast Mode Plus

Unit

Min

Max

tw(SCLL)

tw(SCLH)

tsu(SDA)

th(SDA)

tr(SDA)

tr(SCL)

tf(SDA)

tf(SCL)

th(STA)

tsu(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

Start condition hold time

Repeated Start condition

setup time

4.7

-

1.3

4.0

-

0.6

250

-

100

0(3) 3450(2)

0(3)

-

1000

-

-

300

-

4.0

-

0.6

4.7

-

0.6

tsu(STO) Stop condition setup time

4.0

-

0.6

tw(STO:STA)

Stop to Start condition time

(bus free)

4.7

-

1.3

Cb

Capacitive load for each bus

line

-

400

-

-

-

-

900(2)

300

300

-

-

-

-

400

0.5

0.26

50

0(4)

-

-

0.26

0.26

0.26

0.5

-

-

µs

-

-

450(2)

120

ns

120

-

µs

-

-

μs

-

μs

550

pF

1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when

I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in

production.

2. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region

of the falling edge of SCL.

4. The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region

of the falling edge of SCL.

86/105

Doc ID 022265 Rev 3

Share Link: