STM32F051K6T7 查看數據表（PDF） - STMicroelectronics
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STM32F051K6T7
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STM32F051K6T7 Datasheet PDF : 122 Pages
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STM32F051x4 STM32F051x6 STM32F051x8
Electrical characteristics
Table 52. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
WLATENCY(2)(4)
ADC_DR register ready
latency
ADC clock = HSI14
ADC clock = PCLK/2
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
- cycles + 3
-
fPCLK cycles
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
tlatr(2)
JitterADC
fADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
fADC = fPCLK/4
fADC = fHSI14 = 14 MHz
ADC jitter on trigger
conversion
fADC = fHSI14
0.179
-
0.196
5.5
0.219
10.5
-
1
0.250
-
µs
1/fPCLK
µs
1/fPCLK
µs
1/fHSI14
tS(2)
tSTAB(2)
Sampling time
Stabilization time
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
-
-
fADC = 14 MHz,
12-bit resolution
12-bit resolution
0.107
-
1.5
-
14
1
-
17.1
239.5
18
µs
1/fADC
1/fADC
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
During
on IDD
conversion of the sampled value
should be taken into account.
(12.5
x
ADC
clock
period),
an
additional
consumption
of
100
µA
on
IDDA
and
60
µA
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
Equation 1: RAIN max formula
RAIN < f--A---D----C----×------C-----A---D--T-C---S--×------l-n----(---2---N----+----2---) – RADC
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Ts (cycles)
1.5
7.5
13.5
Table 53. RAIN max for fADC = 14 MHz
tS (µs)
0.11
0.54
0.96
RAIN max (kΩ)(1)
0.4
5.9
11.4
DocID022265 Rev 7
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