AT91SAM9G46B-CU 查看數據表（PDF） - Atmel Corporation

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AT91SAM9G46B-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

48.15.1.2 Timing Conditions

Timings are given assuming a capacitance load on MISO, SPCK and MOSI as defined in Table 48-33.

Table 48-33.

Capacitance Load for MISO, SPCK and MOSI (product dependent)

Corner

Supply

Max

3.3V

40 pF

1.8V

20 pF

Min

5 pF

5 pF

48.15.1.3 Timing Extraction

In Figure 48-7 “SPI Master Mode 1 and 2” and Figure 48-8 “SPI Master Mode 0 and 3”, the MOSI line shifting edge

is represented with a hold time = 0. However, it is important to note that for this device, the MISO line is sampled

prior to the MOSI line shifting edge. As shown in Figure 48-6 “MISO Capture in Master Mode”, the device sampling

point extends the propagation delay (tp) for slave and routing delays to more than half the SPI clock period,

whereas the common sampling point allows only less than half the SPI clock period.

As an example, an SPI Slave working in Mode 0 is safely driven if the SPI Master is configured in Mode 0.

Figure 48-6. MISO Capture in Master Mode

SPCK

(generated

by the master)

0 < delay < SPI0 or SPI3

MISO

(slave answer)

tp

Internal

shift register

Bit N

Bit N+1

Common sampling point

MISO cannot be provided

before the edge

Device sampling point

Safe margin,

always > 0

Extended tp

Bit N

Figure 48-7. SPI Master Mode 1 and 2

SPCK

MISO

MOSI

SPI2

SPI0

SPI1

1228 SAM9G46 Series [DATASHEET]

Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15

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