STM8S003F3 STM8S003K3
7
Interrupt vector mapping
Interrupt vector mapping
IRQ Source
no. block
-
RESET
-
TRAP
0
TLI
1
AWU
2
CLK
3
EXTI0
4
EXTI1
5
EXTI2
6
EXTI3
7
EXTI4
8
-
9
-
10
SPI
11
TIM1
12
TIM1
13
TIM2
14
TIM2
15
-
16
-
17 UART1
18 UART1
19
I2C
20
-
21
-
22
ADC1
23
TIM4
24
Flash
1. Except PA1
Table 11. Interrupt mapping
Description
Wakeup from Wakeup from
Halt mode Active-halt mode
Reset
Yes
Yes
Software interrupt
-
-
External top level interrupt
-
-
Auto wake up from halt
-
Yes
Clock controller
Port A external interrupts
-
Yes(1)
-
Yes(1)
Port B external interrupts
Yes
Yes
Port C external interrupts
Yes
Yes
Port D external interrupts
Yes
Yes
Port E external interrupts
Yes
Yes
Reserved
Reserved
End of transfer
Yes
Yes
TIM1 update/overflow/underflow/
trigger/break
-
-
TIM1 capture/compare
-
-
TIM2 update /overflow
-
-
TIM2 capture/compare
-
-
Reserved
Reserved
Tx complete
-
-
Receive register DATA FULL
-
-
I2C interrupt
Yes
Yes
Reserved
Reserved
ADC1 end of conversion/analog
watchdog interrupt
-
-
TIM4 update/overflow
-
-
EOP/WR_PG_DIS
-
-
Reserved
Vector address
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
0x00 8068
0x00 806C to
0x00 807C
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