PIC16F1503T-I 查看數據表（PDF） - Microchip Technology

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PIC16F1503T-I

14-Pin Flash, 8-Bit Microcontrollers

Microchip Technology 

PIC16(L)F1503

21.4.5 START CONDITION

21.4.7 RESTART CONDITION

The I2C specification defines a Start condition as a

transition of SDAx from a high to a low state while

SCLx line is high. A Start condition is always gener-

ated by the master and signifies the transition of the

bus from an Idle to an Active state. Figure 21-12

shows wave forms for Start and Stop conditions.

A bus collision can occur on a Start condition if the

module samples the SDAx line low before asserting it

low. This does not conform to the I2C Specification that

states no bus collision can occur on a Start.

21.4.6 STOP CONDITION

A Stop condition is a transition of the SDAx line from

low-to-high state while the SCLx line is high.

Note: At least one SCLx low time must appear

before a Stop is valid, therefore, if the SDAx

line goes low then high again while the SCLx

line stays high, only the Start condition is

detected.

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave. Figure 21-13 shows the wave form for a

Restart condition.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop condi-

tion, a high address with R/W clear, or high address

match fails.

21.4.8 START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

FIGURE 21-12: I2C START AND STOP CONDITIONS

SDAx

SCLx

S

Start

Condition

Change of

Data Allowed

FIGURE 21-13: I2C RESTART CONDITION

Change of

Data Allowed

P

Stop

Condition

Change of

Data Allowed

Sr

Restart

Condition

Change of

Data Allowed

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DS40001607D-page 169

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