PIC16(L)F1503
23.0 CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 16
input signals, and through the use of configurable
gates, reduces the 16 inputs to four logic lines that drive
one of eight selectable single-output logic functions.
Input sources are a combination of the following:
• I/O pins
• Internal clocks
• Peripherals
• Register bits
The output can be directed internally to peripherals and
to an output pin.
Refer to Figure 23-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
- OR-XNOR
• Latches
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
FIGURE 23-1:
CONFIGURABLE LOGIC CELL BLOCK DIAGRAM
LCx_in[0]
LCx_in[1]
LCx_in[2]
LCx_in[3]
LCx_in[4]
LCx_in[5]
LCx_in[6]
LCx_in[7]
LCx_in[8]
LCx_in[9]
LCx_in[10]
LCx_in[11]
LCx_in[12]
LCx_in[13]
LCx_in[14]
LCx_in[15]
lcxg1
lcxg2
lcxg3
lcxg4
Logic
Function
(2)
LCxEN
lcxq
LCxMODE<2:0>
LCxPOL
DQ
Q1
Rev. 10-000025A
8/1/2013
LCxOUT
MLCxOUT
LCx_out
to Peripherals
LCxOE
TRIS Control
CLCx
Interrupt
det
LCXINTP
LCXINTN
Interrupt
det
set bit
CLCxIF
Note 1: See Figure 23-2.
2: See Figure 23-3.
DS40001607D-page 214
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