PIC32MX230F128L-I/PF 查看數據表（PDF） - Microchip Technology

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PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 23-12: C1FLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)

bit 20-16 FSEL10<4:0>: FIFO Selection bits

11111 = Reserved

•

•

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

•

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 15

FLTEN9: Filter 9 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL9<4:0>: FIFO Selection bits

11111 = Reserved

•

•

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

•

•

00000 = Message matching filter is stored in FIFO buffer 0

bit 7

FLTEN8: Filter 8 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL8<4:0>: FIFO Selection bits

11111 = Reserved

•

•

•

10000 = Reserved

01111 = Message matching filter is stored in FIFO buffer 15

•

•

•

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 261

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