STM32F100C8H7BTR(2010) 查看數據表（PDF） - STMicroelectronics

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STM32F100C8H7BTR
(Rev.:2010)

Low & medium-density value line, advanced ARM-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

5.3.12 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 33 are derived from tests

performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL

compliant.

Table 33. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Standard I/O input low level voltage

VIL

I/O FT(1) input low level voltage

Standard I/O input high level voltage

VIH

I/O FT(1) input high level voltage

–0.5

–0.5

0.41 (VDD–2)

+1.3

0.42 (VDD–2)

+1

0.28 (VDD–2)

+0.8

0.32 (VDD–2)

+0.75

VDD+0.5

5.5

Standard I/O Schmitt trigger voltage

hysteresis(2)

Vhys

I/O FT Schmitt trigger voltage

hysteresis(2)

200

5% VDD(3)

VSS  VIN  VDD

Standard I/Os

1

Ilkg Input leakage current(4)

VIN = 5 V

I/O FT

3

RPU Weak pull-up equivalent resistor(5)

VIN VSS

30

40

50

RPD

Weak pull-down equivalent

resistor(5)

VIN VDD

30

40

50

CIO I/O pin capacitance

5

1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimum (~10% order).

Unit

V

mV

mV

µA

k

k

pF

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 21 and Figure 22 for standard I/Os, and

in Figure 23 and Figure 24 for 5 V tolerant I/Os.

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Doc ID 16455 Rev 2

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