STM32F100RBH7B 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

STM32F100RBH7B

Low & medium-density value line, advanced ARM®-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

5.3.16

Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Table 39 are derived from tests

performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage

conditions summarized in Table 8.

The STM32F100xx value line I2C interface meets the requirements of the standard I2C

communication protocol with the following restrictions: the I/O pins SDA and SCL are

mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected

between the I/O pin and VDD is disabled, but is still present.

The I2C characteristics are described in Table 39. Refer also to Section 5.3.12: I/O current

injection characteristics for more details on the input/output alternate function characteristics

(SDA and SCL).

Symbol

Table 39. I2C characteristics

Parameter

Standard mode I2C(1) Fast mode I2C(1)(2)

Unit

Min

Max

Min

Max

tw(SCLL)

tw(SCLH)

tsu(SDA)

th(SDA)

tr(SDA)

tr(SCL)

tf(SDA)

tf(SCL)

th(STA)

tsu(STA)

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

Start condition hold time

Repeated Start condition setup

time

4.7

-

1.3

-

µs

4.0

-

0.6

-

250

-

100

-

0

-

0

900(3)

-

1000

-

300

ns

-

300

-

300

4.0

-

0.6

-

µs

4.7

-

0.6

-

tsu(STO) Stop condition setup time

4.0

-

0.6

-

µs

tw(STO:STA)

Stop to Start condition time (bus

free)

4.7

-

1.3

-

µs

Cb

Capacitive load for each bus line

-

400

-

400 pF

1. Guaranteed by design.

2.

faPcChLieK1vemfuasstt

bmeoadteleI2aCstfr2eMquHeznctoieasc. hItiemvuessttbaendaamrdumltiopdleeoIf2C10frMeqHuzetnocireesa.cIht

must be

the 400

at least 4 MHz

kHz maximum

to

I2C

fast mode clock.

3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

64/96

DocID16455 Rev 9

Share Link: