Electrical characteristics
Figure 12. fCPUmax versus VDD
fCPU [MHz]
STM8S207xx, STM8S208xx
24
FUNCTIONALITY
NOT GUARANTEED 16
IN THIS AREA
12
8
4
0
FUNCTIONALITY GUARANTEED
@ TA -40 to 105 °C
FUNCTIONALITY
GUARANTEED
@ TA -40 to 125 °C
2.95
4.0
5.0 5.5
SUPPLY VOLTAGE [V]
10.3.1
Table 19. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
tVDD
tTEMP
VDD rise time rate
VDD fall time rate
Reset release
delay
2(1)
2(1)
VDD rising
VIT+
Power-on reset
threshold
2.65
VIT-
Brown-out reset
threshold
2.58
VHYS(BOR)
Brown-out reset
hysteresis
1. Guaranteed by design, not tested in production.
Typ
2.8
2.73
70
Max Unit
∞
µs/V
∞
1.7(1) ms
2.95 V
2.88 V
mV
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series inductance
to less than 15 nH.
Figure 13. External capacitor CEXT
ESR
C
ESL
Rleak
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
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Doc ID 14733 Rev 12