DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Figure 18. SoC Platform Clocking

Intel® Quark SoC X1000—Clocking

External Device(s)

DDR3_CK/CKB[1:0]

FLEX0_CLK

FLEX1_CLK

FLEX2_CLK

REF[0/1]_OUTCLK_P/N

25 MHz

Primary

Reference

32 kHz RTC Reference

(optional)

Platform

Clock

Inputs and

Outputs

RMII_REF_CLK_OUT

RMII_REF_CLK

DRAM Ranks [0-1]

PCIe* Connector(s)

Ethernet

PHY

(RMII)

I2C* Interface

I2C_CLK

LSPI_SCK

SPI Flash

7.2

SPI Device

SPI[0/1]_SCK

The references required for the various interface PLLS (e.g., USB/PCIe*) and the

processor are internally generated by the Integrated Clocking unit.

Platform/System Clock Domains

The SoC contains multiple clock domains to support its various interfaces. Table 54

and Table 55 summarize the different clock inputs and outputs in the system.

Intel® Quark SoC X1000

DS

100

October 2013

Document Number: 329676-001US

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