DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Inte® Quark SoC X1000—Physical Interfaces

Figure 3.

Signals In Default System Pin List

DDR3_DQ[15:0]

DDR3_DQS[1:0]

DDR3_DQSB[1:0]

DDR3_DM[1:0]

DDR3_MA[15:0]

DDR3_BS[2:0]

DDR3_RASB

DDR3_CASB

DDR3_WEB

DDR3_CSB[1:0]

DDR3_ODT[1:0]

DDR3_CKE[1:0]

DDR3_CK[1:0]

DDR3_CKB[1:0]

DDR3_VREF

DDR3_ODTPU/DQPU/CMDPU

DDR3_IDRAM_PWROK

DDR3_ISYSPWRGOOD

DDR3_DRAMRSTB

MAC[0/1]_TXEN

MAC[0/1]_TXDATA[1:0]

MAC[0/1]_RXDV

MAC[0/1]_RXDATA[1:0]

MAC[0/1]_MDC

MAC[0/1]_MDIO

RMII_REF_CLK

PCIE_PETP[1:0]

PCIE_PETN[1:0]

PCIE_PERP[1:0]

PCIE_PERN[1:0]

PCIE_REFCLKN

PCIE_REFCLKP

PCIE_IRCOMP

PCIE_RBIAS

SD_DATA[7:0]

SD_CMD

SD_CLK

SD_WP

SD_CD_B

SD_LED

SD_PWR

USBD_DP

USBD_DN

USBH[1:0]_DP

USBH[1:0]_DN

USBH[1:0]_OC_B

IUSBCOMP

OUSBCOMP

USBH[1:0]_PWR_EN

FLEX_CLK[2:0]

CKSYS25OUT

RMII_REF_CLK_OUT

REF[0/1]_OUTCLK_P

REF[0/1]_OUTCLK_N

OSC_COMP

XTAL_IN

XTAL_OUT

RTC_EXT_CLK_EN

DDR3

Interface

Ethernet

RMII

Interface

PCI Express* 2.0

Interface

SD/MMC

Interface

Universal Serial

Bus 2.0

Interface

Internal Clocking

CPU

Core

PRDY_B

PREQ_B

TCK

TDI

TDO

TMS

TRST_B

JTAG Port

Legacy

Components

IVCCRTCEXT

RTCX1

RTCX2

RTCRST_B

THERM_B

SMI_B

Legacy Bridge

LSPI_SS_B

LSPI_SCK

LSPI_MISO

LSPI_MOSI

Power

Management

Controller

Interface

HSUART

Interface

RESET_BTN

PWR_BTN

WAKE_B

GPE_B

S5_PG

S3_3V3_EN

S3_1V5_EN

S3_PG

S0_3V3_EN

S0_1V5_EN

S0_1V0_EN

S0_1P0_PG

S0_PG

ODRAM_PWROK

OSYSPWRGOOD

SIU0_DCD_B

SIU0_DSR_B

SIU0_DTR_B

SIU0_RI_B

SIU[0/1]_CTS_B

SIU[0/1]_RTS_B

SIU[0/1]_RXD

SIU[0/1]_TXD

SPI

Interface

I2C*

Interface

GPIO

Interface

SPI[0/1]_SS_B

SPI[0/1]_SCK

SPI[0/1]_MISO

SPI[0/1]_MOSI

I2C_CLK

I2C_DATA

GPIO_SUS[5:0]

GPIO[9:0]

Inte® Quark SoC X1000

DS

46

October 2013

Document Number: 329676-001US

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