DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Inte® Quark SoC X1000—Physical Interfaces
Table 19. JTAG and Debug Interface Signals
Signal Name
TCK
TDI
TDO
TMS
TRST_B
PRDY_B
PREQ_B
Dir Term Power
I 20k(L) 3.3V
I 20k(H) 3.3V
O
Ext
3.3V
I 20k(H) 3.3V
I 20k(H) 3.3V
O
-
3.3V
I 20k(H) 3.3V
Type
CMOS3.3
CMOS3.3
CMOS3.3
CMOS3.3
CMOS3.3
CMOS3.3
CMOS3.3
S4/S5
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
Off
Pull-up
Default Buffer State
S3
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
Off
Pull-up
Reset
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
VoH
Pull-up
Enter S0
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
VoH
Pull-up
2.15
Legacy Interface Signals
See Chapter 19.0, “I2C* Controller/GPIO Controller” and Chapter 21.0, “Legacy
Bridge” for more details of the legacy interface signals.
Table 20. Legacy Interface Signals
Signal Name
CLK14
WAKE_B
GPE_B
THRM_B
SMI_B
Dir Term Power
Type
I
-
3.3V
I 20k(H) 3.3V
I 20k(H) 3.3V
I 20k(H) 3.3V
I 20k(H) 3.3V
CMOS3.3
CMOS3.3_OD
CMOS3.3_OD
CMOS3.3
CMOS3.3
S4/S5
Off
Off
Off
Off
Off
Default Buffer State
S3
Off
Pull-up
Pull-up
Off
Off
Reset
Unknown/
Running
Pull-up
Pull-up
Pull-up
Pull-up
Enter S0
Unknown/
Running
Pull-up
Pull-up
Pull-up
Pull-up
2.16
General Purpose I/O Interface Signals
All GPIOs default to inputs. GPIO_SUS[5:0] are suspend well GPIOs and remain
available in S3. The default buffer state of these GPIOs while in S3 and when entering
S0 from S3 is configuration dependent.
Table 21. General Purpose I/O Signals
Signal Name
GPIO_SUS[5:0]
GPIO[9:0]
Dir Term Power
I/O
-
I/O
-
3.3V
3.3V
Type
CMOS3.3
CMOS3.3
S4/S5
Off
Off
Default Buffer State
S3
Unknown
Off
Reset
ViX
ViX
Enter S0
ViX/Unknown
ViX
Inte® Quark SoC X1000
DS
54
October 2013
Document Number: 329676-001US
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