DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:0

0b

RW

Cycle Data (CD): This field is shifted out during the data portion of the SPI cycle. This

register also shifts in the data during the data portion of the SPI cycle

21.7.4.10 SPI Data 3 - Lower 32 Bits (SPID3_1)—Offset 3040h

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

SPID3_1: [RCBA] + 3040h

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:0

0b

RW

Cycle Data (CD): This field is shifted out during the data portion of the SPI cycle. This

register also shifts in the data during the data portion of the SPI cycle

21.7.4.11 SPI Data 3 - Upper 32 Bits (SPID3_2)—Offset 3044h

Access Method

Type: Memory Mapped I/O Register

(Size: 32 bits)

SPID3_2: [RCBA] + 3044h

RCBA Type: PCI Configuration Register (Size: 32 bits)

RCBA Reference: [B:0, D:31, F:0] + F0h

Default: 00000000h

31

28

24

20

16

12

8

4

0

00000000000000000000000000000000

Bit

Default &

Range Access

Description

31:0

0b

RW

Cycle Data (CD): This field is shifted out during the data portion of the SPI cycle. This

register also shifts in the data during the data portion of the SPI cycle

21.7.4.12 SPI Data 4 - Lower 32 Bits (SPID4_1)—Offset 3048h

Access Method

Intel® Quark SoC X1000

DS

848

October 2013

Document Number: 329676-001US

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