DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
21.7.4.22 Opcode Type Configuration (OPTYPE)—Offset 3076h
This register is not writable when the SPI Configuration Lock-Down bit in the SPI Status
register is set. Entries in this register correspond to the entries in the Opcode Menu
Configuration register. Note that the definition below only provides write protection for
opcodes that have addresses associated with them. Therefore, any erase or write
opcodes that do not use an address should be avoided (for example, Chip Erase. and
Auto-Address Increment Byte Program.).
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
OPTYPE: [RCBA] + 3076h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 0000h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Default &
Range Access
Description
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
0b
RW/L
0b
RW/L
0b
RW/L
0b
RW/L
0b
RW/L
0b
RW/L
0b
RW/L
0b
RW/L
Opcode Type 7 (OT7): See the description for bits 1:0
Opcode Type 6 (OT6): See the description for bits 1:0
Opcode Type 5 (OT5): See the description for bits 1:0
Opcode Type 4 (OT4): See the description for bits 1:0
Opcode Type 3 (OT3): See the description for bits 1:0
Opcode Type 2 (OT2): See the description for bits 1:0
Opcode Type 1 (OT1): See the description for bits 1:0
Opcode Type 0 (OT0): This field specifies information about the corresponding Opcode
0. This information allows the hardware to 1) know whether to use the address field and
2) provide BIOS protection capabilities. The hardware implementation also uses the
read vs. write information for modifying the behavior of the SPI interface logic. The
encoding of the two bits is:
00 = No Address associated with this Opcode and Read Cycle type
01 = No Address associated with this Opcode and Write Cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
21.7.4.23 Opcode Menu Configuration - Lower 32 Bits (OPMENU_1)—Offset
3078h
This register is not writable when the SPI Configuration Lock-Down bit in the SPI Status
register is set. Eight entries are available in this register to give BIOS a sufficient set of
commands for communicating with the flash device, while also restricting what
malicious software can do. This keeps the hardware flexible enough to operate with a
wide variety of SPI devices. It is recommended that BIOS avoid programming Write
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
853
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