DHQ1ECCSECETS1SR1WH 查看數據表（PDF） - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
GIS: [0xFED00000] + 20h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:3
2
1
0
0b
RO
0b
RW/1C
0b
RW/1C
0b
RW/1C
Reserved (RSV): Reserved.
Timer 2 Status (T2): In edge triggered mode, this bit always reads as 0. In level
triggered mode, this bit is set when an interrupt is active.
Timer 1 Status (T1): In edge triggered mode, this bit always reads as 0. In level
triggered mode, this bit is set when an interrupt is active.
Timer 0 Status (T0): In edge triggered mode, this bit always reads as 0. In level
triggered mode, this bit is set when an interrupt is active.
21.9.3.5
Main Counter Value Register - Lower 32 Bits (MCV_1)—Offset F0h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
MCV_1: [0xFED00000] + F0h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:0
0b
RW
Counter Value (CV): Reads return the current value of the lower 32 bits of the counter.
Writes load the new value to the lower 32 bits of the counter.
21.9.3.6
Main Counter Value Register - Upper 32 Bits (MCV_2)—Offset F4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
MCV_2: [0xFED00000] + F4h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
871
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