PIC24HJ32GP304-I/ML 查看數據表（PDF） - Microchip Technology
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PIC24HJ32GP304-I/ML Datasheet PDF : 357 Pages
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
REGISTER 13-2: TxCON: TIMER CONTROL REGISTER (x = 3 OR 5)
R/W-0
U-0
R/W-0
U-0
U-0
U-0
TON(2)
—
TSIDL(1)
—
—
—
bit 15
U-0
U-0
—
—
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
—
TGATE(2)
TCKPS<1:0>(2)
—
bit 7
U-0
R/W-0
U-0
—
TCS(2)
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
TON: Timery On bit(2)
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(1)
1 = Discontinue timer operation when device enters Idle mode
0 = Continue timer operation in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
TCKPS<1:0>: Timerx Input Clock Prescale Select bits(2)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(2)
1 = External clock from TxCK pin
0 = Internal clock (FOSC/2)
Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits
have no effect.
© 2009 Microchip Technology Inc.
Preliminary
DS70293D-page 167
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