PIC24HJ64GP802-I/SP 查看數據表（PDF） - Microchip Technology

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PIC24HJ64GP802-I/SP

High-Performance, 16-bit Microcontrollers

Microchip Technology 

TABLE 4-28: PORTA REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Bit 9

Bit 8 Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

TRISA

02C0

—

—

—

—

—

TRISA10 TRISA9 TRISA8 TRISA7

—

PORTA

02C2

—

—

—

—

—

RA10

RA9

RA8

RA7

—

LATA

02C4

—

—

—

—

—

LATA10

LATA9

LATA8 LATA7

—

ODCA

02C6

—

—

—

—

—

ODCA10 ODCA9 ODCA8 ODCA7

—

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

—

TRISA4 TRISA3 TRISA2

—

RA4

RA3

RA2

—

LATA4

LATA3 LATA2

—

—

—

—

Bit 1

TRISA1

RA1

LATA1

—

Bit 0

TRISA0

RA0

LATA0

—

All

Resets

079F

xxxx

xxxx

0000

TABLE 4-29: PORTB REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

TRISB

PORTB

LATB

ODCB

Legend:

02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7

02CA RB15

RB14

RB13

RB12

RB11

RB10

RB9

RB8

RB7

02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7

02CE

—

—

—

—

ODCB11 ODCB10 ODCB9 ODCB8 ODCB7

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 6

TRISB6

RB6

LATB6

ODCB6

Bit 5

TRISB5

RB5

LATB5

ODCB5

Bit 4

TRISB4

RB4

LATB4

—

Bit 3

TRISB3

RB3

LATB3

—

Bit 2

TRISB2

RB2

LATB2

—

Bit 1

Bit 0

TRISB1

RB1

LATB1

—

TRISB0

RB0

LATB0

—

All

Resets

FFFF

xxxx

xxxx

0000

TABLE 4-30: PORTC REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Bit 9

Bit 8 Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

TRISC

PORTC

LATC

ODCC

Legend:

02D0

—

—

—

—

—

—

TRISC9 TRISC8 TRISC7

02D2

—

—

—

—

—

—

RC9

RC8

RC7

02D4

—

—

—

—

—

—

LATC9 LATC8 LATC7

02D6

—

—

—

—

—

—

ODCC9 ODCC8 ODCC7

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TRISC6

RC6

LATC6

ODCC6

TRISC5

RC5

LATC5

ODCC5

TRISC4

RC4

LATC4

ODCC4

TRISC3

RC3

LATC3

ODCC3

TRISC2

RC2

LATC2

—

Bit 1

TRISC1

RC1

LATC1

—

Bit 0

TRISC0

RC0

LATC0

—

All

Resets

03FF

xxxx

xxxx

0000

TABLE 4-31: SYSTEM CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13

Bit 12

Bit 11 Bit 10 Bit 9 Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2

Bit 1

Bit 0

All

Resets

RCON

OSCCON

CLKDIV

PLLFBD

OSCTUN

Legend:

Note 1:

2:

0740 TRAPR IOPUWR —

—

—

—

CM VREGS EXTR

SWR

0742 —

COSC<2:0>

—

NOSC<2:0>

CLKLOCK IOLOCK

0744 ROI

DOZE<2:0>

DOZEN

FRCDIV<2:0>

PLLPOST<1:0>

0746 —

—

—

—

—

—

—

0748 —

—

—

—

—

—

—

—

—

—

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

RCON register Reset values dependent on type of Reset.

OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.

SWDTEN WDTO SLEEP IDLE

BOR

LOCK

—

CF

— LPOSCEN

—

PLLPRE<4:0>

PLLDIV<8:0>

TUN<5:0>

POR

OSWEN

xxxx(1)

0300(2)

3040

0030

0000

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