AT90PWM2B-16SU 查看數據表（PDF） - Atmel Corporation

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AT90PWM2B-16SU

8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

Figure 18-1. USART Block Diagram(1)

UBRR[H:L]

BAUD RATE GENERATOR

UDR (Transmit)

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

UDR (Receive)

AT90PWM2/3/2B/3B

CLKio

Clock Generator

SYNC LOGIC

PARITY

GENERATOR

CLOCK

RECOVERY

DATA

RECOVERY

PARITY

CHECKER

PIN

CONTROL

XCK

Transmitter

TX

CONTROL

PIN

CONTROL

TxD

Receiver

RX

CONTROL

PIN

CONTROL

RxD

UCSRA

UCSRB

UCSRC

Note: 1. Refer to Pin Configurations3, Table 11-9 on page 75, and Table 11-7 on page 73 for USART

pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only

used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial

Shift Register, Parity Generator and Control logic for handling different serial frame formats. The

write buffer allows a continuous transfer of data without any delay between frames. The

Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

18.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

4317K–AVR–03/2013

186

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