DSPIC33FJ64GP706AE/PF 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ64GP706AE/PF

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJXXXGPX06A/X08A/X10A

11.0 I/O PORTS

Note 1: This data sheet summarizes the features

of the dsPIC33FJXXXGPX06A/X08A/

X10A family of devices. However, it is not

intended to be a comprehensive refer-

ence source. To complement the

information in this data sheet, refer to

Section 10. “I/O Ports” (DS70193) in

the

“dsPIC33F/PIC24H

Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKIN) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

11.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 11-1 illus-

trates how ports are shared with other peripherals and

the associated I/O pin to which they are connected.

When a peripheral is enabled and actively driving an

associated pin, the use of the pin as a general purpose

output pin is disabled. The I/O pin may be read, but the

output driver for the parallel port bit will be disabled. If

a peripheral is enabled, but the peripheral is not

actively driving a pin, that pin may be driven by a port.

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch. Reads from the port

(PORTx), read the port pins, while writes to the port

pins, write the latch.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pins will read as zeros.

When a pin is shared with another peripheral or

function that is defined as an input only, it is

nevertheless regarded as a dedicated port because

there is no other competing source of outputs. An

example is the INT4 pin.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O

1 Output Enable

0

PIO Module

Read TRIS

1 Output Data

0

Data Bus

WR TRIS

WR LAT +

WR PORT

Read LAT

DQ

CK

TRIS Latch

D

Q

CK

Data Latch

Read Port

I/O Pin

Input Data

© 2011 Microchip Technology Inc.

DS70593C-page 167

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