DSPIC33FJ128GP310AI/MR 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ128GP310AI/MR

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology

DSPIC33FJ128GP310AI/MR Datasheet PDF : 350 Pages

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TABLE 4-24: DCI REGISTER MAP

SFR

Name

Addr. Bit 15 Bit 14

Bit 13

Bit 12 Bit 11 Bit 10

Bit 9

Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Bit 1

Bit 0

Reset State

DCICON1

DCICON2

DCICON3

DCISTAT

TSCON

RSCON

RXBUF0

RXBUF1

RXBUF2

RXBUF3

TXBUF0

TXBUF1

TXBUF2

TXBUF3

Legend:

Note 1:

0280 DCIEN —

DCISIDL

— DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST —

—

0282 —

—

— BLEN1 BLEN0

—

COFSG<3:0>

—

0284 —

—

BCG<11:0>

0286 —

—

— SLOT3 SLOT2 SLOT1 SLOT0 —

—

— ROV

0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3

028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3

0290

Receive Buffer #0 Data Register

0292

Receive Buffer #1 Data Register

0294

Receive Buffer #2 Data Register

0296

Receive Buffer #3 Data Register

0298

Transmit Buffer #0 Data Register

029A

Transmit Buffer #1 Data Register

029C

Transmit Buffer #2 Data Register

029E

Transmit Buffer #3 Data Register

— = unimplemented, read as ‘0’.

Refer to the “dsPIC33F/PIC24H Family Reference Manual” for descriptions of register bit fields.

— COFSM1 COFSM0 0000 0000 0000 0000

WS<3:0>

0000 0000 0000 0000

RFUL TUNF TMPTY 0000 0000 0000 0000

TSE2 TSE1

TSE0 0000 0000 0000 0000

RSE2 RSE1

RSE0 0000 0000 0000 0000

0000 0000 0000 0000

TABLE 4-25: PORTA REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10

Bit 9

Bit 8 Bit 7 Bit 6

Bit 5

TRISA

PORTA

LATA

ODCA(2)

Legend:

Note 1:

02C0 TRISA15 TRISA14 TRISA13 TRISA12

—

TRISA10 TRISA9

—

TRISA7 TRISA6 TRISA5

02C2 RA15

RA14

RA13

RA12

—

RA10

RA9

—

RA7

RA6

RA5

02C4 LATA15 LATA14 LATA13 LATA12

—

LATA10 LATA9

—

LATA7 LATA6 LATA5

06C0 ODCA15 ODCA14

—

ODCA5

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.

The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

Bit 4

TRISA4

RA4

LATA4

ODCA4

Bit 3

Bit 2

TRISA3

RA3

LATA3

ODCA3

TRISA2

RA2

LATA2

ODCA2

Bit 1

TRISA1

RA1

LATA1

ODCA1

Bit 0

All

Resets

TRISA0

RA0

LATA0

ODCA0

F6FF

xxxx

0000

TABLE 4-26: PORTB REGISTER MAP(1)

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

TRISB

PORTB

LATB

Legend:

Note 1:

02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5

02C8 RB15

RB14

RB13

RB12

RB11

RB10

RB9

RB8

RB7

RB6

RB5

02CA LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.

The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.

Bit 4

TRISB4

RB4

LATB4

Bit 3

Bit 2

Bit 1

Bit 0

TRISB3

RB3

LATB3

TRISB2

RB2

LATB2

TRISB1

RB1

LATB1

TRISB0

RB0

LATB0

All

Resets

FFFF

xxxx

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