dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
FIGURE 22-2:
ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32MC302,
dsPIC33FJ64MC202/802 AND dsPIC33FJ128MC202/802 DEVICES
AN0
AN5
CHANNEL
SCAN
+
CH0SA<4:0>
CH0SB<4:0>
-
CH0
CSCNA
AN1
VREFL
S/H0
CH0NA CH0NB
AN0
AN3
+
CH1(2)
CH123SA CH123SB
-
VREFL
CH123NA CH123NB
AN1
AN4
CH2(2)
+
CH123SA CH123SB
-
S/H1
VREF+(1) AVDD VREF-(1) AVSS
S/H2
VCFG<2:0>
VREFH
VREFL
SAR ADC
ADC1BUF0
VREFL
CH123NA CH123NB
AN2
AN5
CH3(2)
+
CH123SA CH123SB
-
S/H3
VREFL
CH123NA CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
© 2007-2012 Microchip Technology Inc.
DS70291G-page 283