Symbol
fADC
fS(1)
fTRIG(1)
VAIN
RAIN(1)
CADC(1)
tSTAB(1)
tCAL(1)
tlatr(1)
tlatrinj(1)
Table 68. ADC characteristics (continued)
Parameter
Conditions
Min
ADC clock frequency
Sampling rate
External trigger frequency
Conversion voltage range(2)
External input impedance
Internal sample and hold capacitor
-
Resolution = 12 bits,
Fast Channel
Resolution = 10 bits,
Fast Channel
Resolution = 8 bits,
Fast Channel
Resolution = 6 bits,
Fast Channel
fADC = 72 MHz
Resolution = 12 bits
Resolution = 12 bits
-
-
-
0.14
0.01
0.012
0.014
0.0175
-
-
0
-
-
Power-up time
-
Calibration time
fADC = 72 MHz
-
CKMODE = 00
1.5
Trigger conversion latency
CKMODE = 01
-
Regular and injected channels
without conversion abort
CKMODE = 10
-
CKMODE = 11
-
CKMODE = 00
2.5
Trigger conversion latency
CKMODE = 01
-
Injected channels aborting a regular
conversion
CKMODE = 10
-
CKMODE = 11
-
Typ
-
-
-
-
-
-
-
-
-
5
1
1.56
112
2
-
-
-
3
-
-
-
Max
72
5.14
6
7.2
9
5.14
14
VREF+
100
-
2.5
2
2.25
2.125
3.5
3
3.25
3.125
Unit
MHz
MSPS
MHz
1/fADC
V
kΩ
pF
conversion
cycle
µs
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC
1/fADC