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CSR8635 查看數據表(PDF) - CSR plc

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CSR8635 Datasheet PDF : 105 Pages
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As with Long Frame Sync, CSR8635 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT
on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position
or on the rising edge.
9.3.4 Multi-slot Operation
More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO connections are
carried over any of the first 4 slots.
LONG_PCM_SYNC
Or
SHORT_PCM_SYNC
9CchS.a3Rn.8n56e3ls5aQGPreCPFPCCMNaCPPPMc_MICCiCcSP_sP_IMMeYMOnCCrcs_N_eU_LoMtsIOCCpKNeTFme_UaLirdIgpNKTrfDCueaawaordrtNehceiDboetfel9ooen.rN111wtqh3oiiti:tnshCMg22matbuhroeoletdi-Gke3311selCoivstIBe,c22O441naop.CnzsFehf33htiiraagg55oannuutundirroe44eea-nldr669ed.w.x551sict4yhe77:nl26pG6choSC8ri8nloIo77tnIt.nsoct8ouea118smrnfad2.ccB811e22n+-b-Dit22FIC33SriodD33maNBy44p2,taiC44mSnhedia55npen55gndteeinSlm66ta66ebmrefapr7777cl2ee7s.8,T8882h0eD1DCo2ao3rNeN6oto4tkCbaprse B
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.
9.3.6 Slots and Sample Formats
CSR8635 QFN receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are
either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats.
16 clock cycles for 8-bit, 13-bit or 16-bit sample formats.
CSR8635 QFN supports:
13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
A sample rate of 8ksps.
Little or big endian bit order.
For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a
programmable 3-bit audio attenuation compatible with some codecs.
Production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 48 of 105
CS-303725-DSP5
www.csr.com

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