M95256-DRCS3G/AB 查看數據表（PDF） - STMicroelectronics

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M95256-DRCS3G/AB

256 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Connecting to the SPI bus

M95256-DR, M95256, M95256-W, M95256-R

the transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S line is pulled high): this ensures that S and C do not become high at the same

time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.

7.1

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

● CPOL=0, CPHA=0

● CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 18, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

● C remains at 0 for (CPOL=0, CPHA=0)

● C remains at 1 for (CPOL=1, CPHA=1)

Figure 18. SPI modes supported

CPOL CPHA

0

0

C

1

1

C

D

MSB

Q

MSB

AI01438B

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Doc ID 12276 Rev 11

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