ST7PLITEU09M3TR 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

ST7PLITEU09M3TR

8-bit MCU with single voltage Flash memory, ADC, timers

STMicroelectronics 

ST7LITEU05 ST7LITEU09

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

Figure 21. Using the AVD to Monitor VDD

VDD

VIT+(AVD)

Early Warning Interrupt

(Power has dropped, MCU not

not yet in reset)

Vhyst

VIT-(AVD)

VIT+(LVD)

VIT-(LVD)

AVDF bit

0

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

LVD RESET

1

RESET

INTERRUPT Cleared by

reset

1

0

INTERRUPT Cleared by

hardware

8.4.3 Low Power Modes

Mode

WAIT

HALT

Description

No effect on SI. AVD interrupts cause the

device to exit from Wait mode.

The SICSR register is frozen.

The AVD remains active but the AVD inter-

rupt cannot be used to exit from Halt mode.

8.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if

the corresponding Enable Control Bit (AVDIE) is

set and the interrupt mask in the CC register is re-

set (RIM instruction).

Interrupt Event

AVD event

Event

Flag

AVDF

Enable

Control

Bit

AVDIE

Exit

from

Wait

Yes

Exit

from

Halt

No

36/115

1

Share Link: