ST7PLITEU09M3TR 查看數據表（PDF） - STMicroelectronics

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ST7PLITEU09M3TR

8-bit MCU with single voltage Flash memory, ADC, timers

STMicroelectronics 

ST7LITEU05 ST7LITEU09

Figure 32. I/O Port General Block Diagram

REGISTER

ACCESS

ALTERNATE

OUTPUT

1

0

ALTERNATE

ENABLE

DR

DDR

OR

OR SEL

If implemented

DDR SEL

DR SEL

1

0

EXTERNAL

INTERRUPT

SOURCE (eix)

POLARITY

SELECTION

FROM

OTHER

BITS

VDD

P-BUFFER

(see table below)

PULL-UP

(see table below)

VDD

PULL-UP

CONDITION

PAD

N-BUFFER

CMOS

SCHMITT

TRIGGER

DIODES

(see table below)

ANALOG

INPUT

ALTERNATE

INPUT

Table 15. I/O Port Mode Options

Input

Output

Configuration Mode

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Open Drain (logic level)

Legend:NI - not implemented

Off - implemented not activated

On - implemented and activated

Pull-Up

Off

On

Off

P-Buffer

Off

On

Off

Diodes

to VDD

to VSS

On

On

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