ST7PLITEU09M3TR 查看數據表（PDF） - STMicroelectronics
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ST7PLITEU09M3TR Datasheet PDF : 115 Pages
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ST7LITEU05 ST7LITEU09
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped). Refer to Section 13.4.2 Internal RC
oscillator supply characteristics.
13.4.1 Supply Current
TA = -40 to +125°C unless otherwise specified
Symbol
Parameter
Supply current in RUN mode 1)
Supply current in WAIT mode 2)
Supply current in SLOW mode 3)
Supply current in SLOW-WAIT mode 4)
Supply current in AWUFH mode 5)6)
Supply current in ACTIVE HALT mode
IDD Supply current in HALT mode 7)
Supply current in RUN mode 1)
Supply current in WAIT mode 2)
Supply current in SLOW mode 3)
Supply current in SLOW-WAIT mode 4)
Supply current in AWUFH mode 5)6)
Supply current in ACTIVE HALT mode
Supply current in HALT mode 7)
Conditions
fCPU = 4 MHz
fCPU = 8 MHz
fCPU = 4 MHz
fCPU = 8 MHz
fCPU/32 = 250 kHz
fCPU/32 = 250 kHz
TA=85°C
TA=125°C
fCPU = 4 MHz
fCPU = 4 MHz
fCPU/32 = 250 kHz
fCPU/32 = 250 kHz
TA=85°C
TA=125°C
Typ
2.5
5.0
0.85
1.2
600
450
45
100
0.5
0.5
1.30
0.36
300
250
20
90
0.25
0.25
Max
4.58)
7.5
2.08)
3.5
950
750
1008)
250
3.0
5.0
2.0 8)
0.5 8)
4008)
3508)
50 8)
1508)
2.5 8)
4.5 8)
Unit
mA
µA
mA
µA
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
6. This consumption refers to the Halt period only and not the associated run period which is software dependent.
7. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
8. Data based on characterization, not tested in production.
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