Memory and register map
STM8AF61xx, STM8AF62xx
Table 13. General hardware register map (continued)
Address
Block
Register label
Register name
0x00 540B
ADC_LTRL
ADC low threshold register low
0x00 540C
ADC _AWSRH ADC watchdog status register high
0x00 540D
ADC
ADC_AWSRL
ADC watchdog status register low
0x00 540E
ADC _AWCRH ADC watchdog control register high
0x00 540F
ADC _AWCRH ADC watchdog control register low
0x00 5410 to
0x00 541F
Reserved area (16 bytes)
1. Depends on the previous reset source.
2. Write only register.
Reset
status
0x00
0x00
0x00
0x00
0x00
Table 14. CPU/SWIM/debug module/interrupt controller registers
Address
Block
Register label
Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
0x00 7F0B to
0x00 7F5F
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76 to
0x00 7F79
0x00 7F80
CPU(1)
CPU
ITC
SWIM
A
PCE
PCH
PCL
XH
XL
YH
YL
SPH
SPL
CC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
SWIM_CSR
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
Stack pointer low
Condition code register
Reserved area (85 bytes)
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Reserved area (4 bytes)
SWIM control status register
Reset
status
0x00
0x00
0x80
0x00
0x00
0x00
0x00
0x00
0x17(2)
0xFF
0x28
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
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Doc ID 14952 Rev 6