DSPIC33FJ32GP802-I/SP 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ32GP802-I/SP

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0

—

bit 15

U-0

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

—

AMSK9

R/W-0

AMSK8

bit 8

R/W-0

AMSK7

bit 7

R/W-0

AMSK6

R/W-0

AMSK5

R/W-0

AMSK4

R/W-0

AMSK3

R/W-0

AMSK2

R/W-0

AMSK1

R/W-0

AMSK0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSKx: Mask for Address Bit x Select bit

1 = Enable masking for bit x of incoming message address; bit match not required in this position

0 = Disable masking for bit x; bit match required in this position

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 213

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