DSPIC33FJ64GP204T-I/SO 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ64GP204T-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)

bit 3

SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)

When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’

1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0 = Samples multiple channels individually in sequence

bit 2

ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion. SAMP bit is auto-set

0 = Sampling begins when SAMP bit is set

bit 1

SAMP: ADC Sample Enable bit

1 = ADC sample/hold amplifiers are sampling

0 = ADC sample/hold amplifiers are holding

If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000,

automatically cleared by hardware to end sampling and start conversion.

bit 0

DONE: ADC Conversion Status bit

1 = ADC conversion cycle is completed.

0 = ADC conversion not started or in progress

Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear

DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in

progress. Automatically cleared by hardware at start of a new conversion.

DS70292D-page 258

Preliminary

 2009 Microchip Technology Inc.

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