DSPIC33FJ64GP204T-I/SO 查看數據表（PDF） - Microchip Technology

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DSPIC33FJ64GP204T-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

22.4 DAC Clock

The DAC clock signal clocks the internal logic of the

Audio DAC module. The data sample rate of the Audio

DAC is an integer division of the rate of the DAC clock.

The DAC clock is generated via a clock divider circuit

that accepts an auxiliary clock from the auxiliary

oscillator.

The divisor ratio is programmed by clock divider bits

(DACFDIV<6:0>) in the DAC Control register

(DAC1CON). The resulting DAC clock must not exceed

25.6 MHz. If lower sample rates are to be used, then

the DAC filter clock frequency may be reduced to

reduce power consumption. The DAC clock frequency

is 256 times the sampling frequency.

FIGURE 22-1:

BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER

Right Channel

DAC1RDAT

CONTROL

ACLK

DACFDIV<6:0>

CLK DIV

D/A

Note 1

DACDFLT

Amp

DAC1RM

DAC1RP

DAC1RN

DAC1LDAT

D/A

Note 1

Amp

Note 1: If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register.

FIGURE 22-2:

AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED)

0xFFFF

DAC input

Count (DAC1RDAT)

DAC1LM

DAC1LP

DAC1LN

Left Channel

0x0000

VDACH

VDACM

Positive DAC

Output (DAC1RP)

VDACL

VDACH

Negative DAC VDACM

Output (DAC1RN)

VDACL

Note: VOD+ = VDACH – VDACL, VOD- = VDACL – VDACH; refer to Audio DAC Module Specifications, Table 30-42, for typical values.

DS70292D-page 266

Preliminary

 2009 Microchip Technology Inc.

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