ST72324BLJ2B5 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

ST72324BLJ2B5

3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

STMicroelectronics 

ST72324Lxx

CLOCK CHARACTERISTICS (Cont’d)

12.5.5 PLL Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(PLL)

PLL Operating Range

2.85

3.6

V

fOSC

PLL input frequency range

2

4

MHz

∆ fCPU/fCPU Instantaneous PLL jitter 1)

fOSC = 4 MHz. (fCPU=8MHz.)

3.5

5.5

%

Note:

1. Instantaneous PLL jitter is the absolute maximum deviation on a single clock period. Data characterized, not tested in

production.

Figure 64. PLL Clock Jitter vs. Application

Signal frequency1

0.8

0.7

FLASH

0.6

DEVICES

0.5

ROM

0.4

DEVICES

0.3

0.2

0.1

0

2000 1000

500

250

125

Application Signal Frequency (KHz)

PLL clock jitter may cause application errors if high

frequency signals are input or output by the appli-

cation (e.g. high speed serial I/O or sampling of

high frequency signals).

Using the PLL increases clock jitter, however this

is a periodic effect which is absorbed over several

CPU cycles. The lower the frequency of the appli-

cation signal, the less the impact.

Figure 64 shows the effect of jitter (with and with-

out PLL) on application signals in the range

125kHz to 2MHz. At frequencies of less than

125kHz, the jitter is negligible.

Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C

119/154

1

Share Link: