QL8150-8PS484M(2002) 查看數據表（PDF） - QuickLogic Corporation

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QL8150-8PS484M
(Rev.:2002)

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

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The basic power equation which best models power consumption is given below:

PTOTAL = 0.350 + f[0.0031 ηLC + 0.0948 ηCKBF + 0.01 ηCLBF+ 0.0263 ηCKLD+

0.543 ηRAM + 0.20 ηPLL+ 0.0035 ηINP + 0.0257 ηOUTP] (mW)

Where

• ηLC is the total number of logic cells in the design

• ηCKBF = # of clock buffers

• ηCLBF = # of column clock buffers

• ηCKLD = # of loads connected to the column clock buffers

• ηRAM = # of RAM blocks

• ηPLL = # of PLLs

• ηINP is the number of input pins

• ηOUTP is the number of output pins

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VCCIO

VCC

(VCCIO -VCC)MAX

VCC

400 us

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The following requirements must be met when powering up a device (refer to )LJXUH ):

• When ramping up the power supplies keep (VCCIO -VCC)MAX ≤ 500 mV. Deviation from this

recommendation can cause permanent damage to the device.

• VCCIO must lead VCC when ramping the device.

• The power supply must be greater than or equal to 400 µs to reach VCC. Ramping to

VCC/VCCIO before reaching 400 µs can cause the device to behave improperly.

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