ATA6612C-PLQW 查看數據表（PDF） - Atmel Corporation

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ATA6612C-PLQW

8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Atmel Corporation 

• XCK/T0/PCINT20 – Port D, Bit 4

XCK, USART external clock.

T0, Timer/Counter0 counter source.

PCINT20: Pin change interrupt source 20. The PD4 pin can serve as an external interrupt source.

• INT1/OC2B/PCINT19 – Port D, Bit 3

INT1, external interrupt source 1: The PD3 pin can serve as an external interrupt source.

OC2B, output compare match output: The PD3 pin can serve as an external output for the Timer/Counter0 compare match

B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The OC2B pin is also the output

pin for the PWM mode timer function.

PCINT19: Pin change interrupt source 19. The PD3 pin can serve as an external interrupt source.

• INT0/PCINT18 – Port D, Bit 2

INT0, external interrupt source 0: The PD2 pin can serve as an external interrupt source.

PCINT18: Pin change interrupt source 18. The PD2 pin can serve as an external interrupt source.

• TXD/PCINT17 – Port D, Bit 1

TXD, transmit data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an

output regardless of the value of DDD1.

PCINT17: Pin change interrupt source 17. The PD1 pin can serve as an external interrupt source.

• RXD/PCINT16 – Port D, Bit 0

RXD, receive data (Data input pin for the USART). When the USART receiver is enabled this pin is configured as an input

regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the

PORTD0 bit.

PCINT16: Pin change interrupt source 16. The PD0 pin can serve as an external interrupt source.

Table 5-39 and Table 5-40 on page 91 relate the alternate functions of Port D to the overriding signals shown in

Figure 5-26 on page 82.

Table 5-39. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PUOE

PUO

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

PD7/AIN1/PCINT23

0

0

0

0

0

0

PCINT23 × PCIE2

1

PD6/AIN0/OC0A/PCINT22

0

0

0

0

OC0A ENABLE

OC0A

PCINT22 × PCIE2

1

PD5/T1/OC0B/PCINT21

0

0

0

0

OC0B ENABLE

OC0B

PCINT21 × PCIE2

1

DI

PCINT23 INPUT

PCINT22 INPUT

PCINT21 INPUT

T1 INPUT

AIO

AIN1 INPUT

AIN0 INPUT

–

PD4/XCK/T0/PCINT20

0

0

0

0

UMSEL

XCK OUTPUT

PCINT20 × PCIE2

1

PCINT20 INPUT

XCK INPUT

T0 INPUT

–

90 ATA6612C/ATA6613C [DATASHEET]

9111L–AUTO–11/14

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