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EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family

High-Speed I/O Standards Support

7–11

Figure 7–6 shows a RSDS, mini-LVDS, or PPDS interface with two singled-ended

output buffers and external resistors.

Figure 7–6. RSDS, Mini-LVDS, or PPDS Interface with External Resistor Network on the Top and Bottom I/O Banks (1)

Cyclone III Device Family

Emulated RSDS,

Mini-LVDS, or PPDS

Transmitter

Resistor Network

RS

RP

RS

50 Ω

50 Ω

RSDS, Mini-LVDS,

or PPDS Receiver

100 Ω

Note to Figure 7–6:

(1) RS = 120 ; RP = 170 

A resistor network is required to attenuate the output voltage swing to meet RSDS,

mini-LVDS, and PPDS specifications when using emulated transmitters. You can

modify the resistor network values to reduce power or improve the noise margin.

The resistor values chosen must satisfy Equation 7–1.

Equation 7–1.

-R----S---------R-----2----P-- = 50 

RS

+

R-----P-

2

1 Altera recommends that you perform simulations using Cyclone III device family IBIS

models to validate that custom resistor values meet the RSDS, mini-LVDS, or PPDS

requirements.

You can use a single external resistor instead of using three resistors in the resistor

network for an RSDS interface, as shown in Figure 7–7. The external single-resistor

solution reduces the external resistor count while still achieving the required

signaling level for RSDS. However, the performance of the single-resistor solution is

lower than the performance with the three-resistor network.

December 2011 Altera Corporation

Cyclone III Device Handbook

Volume 1

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