EP3C5E324A8ES 查看數據表（PDF） - Altera Corporation

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EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

Chapter 8: External Memory Interfaces in the Cyclone III Device Family

8–9

Cyclone III Device Family Memory Interfaces Pin Support

Figure 8–2. DQS, CQ, or CQ# Pins in Cyclone III Device Family I/O Banks (1)

DQS2L/CQ3L

DQS0L/CQ1L

DQS1L/CQ1L#

DQS3L/CQ3L#

I/O Bank 8

I/O Bank 7

Cyclone III Device Family

I/O Bank 3

I/O Bank 4

DQS2R/CQ3R

DQS0R/CQ1R

DQS1R/CQ1R#

DQS3R/CQ3R#

Note to Figure 8–2:

(1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone III device family except devices in 144-pin EQFP and 164-pin

MBGA.

Figure 8–3 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O

banks of the Cyclone III device in the 144-pin EQFP and 164-pin MBGA packages

only.

Figure 8–3. DQS, CQ, or CQ# Pins for Devices in the 144-Pin EQFP and 164-Pin MBGA Packages

DQS0L/CQ1L

DQS1L/CQ1L#

I/O Bank 8

I/O Bank 7

Cyclone III Devices

in 144-pin EQFP and

164-pin MBGA

I/O Bank 3

I/O Bank 4

DQS0R/CQ1R

DQS1R/CQ1R#

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 1

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