EP3C5E324A8ES 查看數據表（PDF） - Altera Corporation

零件编号

产品描述 (功能)

生产厂家

EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

5–14

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Feedback Modes

Figure 5–10 shows a waveform example of the phase relationship of the PLL clocks in

this mode.

Figure 5–10. Phase Relationship Between PLL Clocks in Normal Mode

Phase Aligned

PLL Reference

Clock at the Input pin

PLL Clock at the

Register Clock Port

External PLL Clock

Outputs (1)

Note to Figure 5–10:

(1) The external clock output can lead or lag the PLL internal clock signals.

Zero Delay Buffer Mode

In zero delay buffer (ZDB) mode, the external clock output pin is phase-aligned with

the clock input pin for zero delay through the device. When using this mode, use the

same I/O standard on the input clock and output clocks to guarantee clock alignment

at the input and output pins.

Figure 5–11 shows an example waveform of the phase relationship of the PLL clocks

in ZDB mode.

Figure 5–11. Phase Relationship Between PLL Clocks in ZDB Mode

Phase Aligned

PLL Reference Clock

at the Input Pin

PLL Clock

at the Register Clock Port

External PLL Clock Output

at the Output Pin

Cyclone III Device Handbook

Volume 1

July 2012 Altera Corporation

Share Link: