PIC16F913/914/916/917/946
TABLE 2-4: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 3
180h
181h
182h
183h
184h
185h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
PCL
Program Counter (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
FSR
TRISF(3)
Indirect Data Memory Address Pointer
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
41,226
33,227
40,226
32,226
41,226
81,228
186h
187h
188h
189h
TRISB
TRISG(3)
PORTF(3)
PORTG(3)
TRISB7
—
RF7
—
TRISB6
—
RF6
—
TRISB5
TRISG5
RF5
RG5
TRISB4
TRISG4
RF4
RG4
TRISB3
TRISG3
RF3
RG3
TRISB2
TRISG2
RF2
RG2
TRISB1
TRISG1
RF1
RG1
TRISB0
TRISG0
RF0
RG0
1111 1111
--11 1111
xxxx xxxx
--xx xxxx
54,227
84,228
81,228
84,228
18Ah
18Bh
18Ch
PCLATH
INTCON
EECON1
—
GIE
EEPGD
—
PEIE
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
—
WRERR WREN
WR
RD
---0 0000
0000 000x
0--- x000
40,226
34,226
189,229
18Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ----
187
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
—
Reserved
—
Reserved
LCDDATA12(3) SEG31
COM0
LCDDATA13(3) SEG39
COM0
LCDDATA14(3)
—
SEG30
COM0
SEG38
COM0
—
LCDDATA15(3)
LCDDATA16(3)
LCDDATA17(3)
SEG31
COM1
SEG39
COM1
—
SEG30
COM1
SEG38
COM1
—
LCDDATA18(3)
LCDDATA19(3)
LCDDATA20(3)
SEG31
COM2
SEG39
COM2
—
SEG30
COM2
SEG38
COM2
—
LCDDATA21(3)
LCDDATA22(3)
LCDDATA23(3)
SEG31
COM3
SEG39
COM3
—
SEG30
COM3
SEG38
COM3
—
LCDSE3(2, 3)
LCDSE4(2, 3)
LCDSE5(2, 3)
SE31
SE39
—
SE30
SE38
—
SEG29
COM0
SEG37
COM0
—
SEG29
COM1
SEG37
COM1
—
SEG29
COM2
SEG37
COM2
—
SEG29
COM3
SEG37
COM3
—
SE29
SE37
—
SEG28
COM0
SEG36
COM0
—
SEG28
COM1
SEG36
COM1
—
SEG28
COM2
SEG36
COM2
—
SEG28
COM3
SEG36
COM3
—
SE28
SE36
—
SEG27
COM0
SEG35
COM0
—
SEG27
COM1
SEG35
COM1
—
SEG27
COM2
SEG35
COM2
—
SEG27
COM3
SEG35
COM3
—
SE27
SE35
—
SEG26
COM0
SEG34
COM0
—
SEG26
COM1
SEG34
COM1
—
SEG26
COM2
SEG34
COM2
—
SEG26
COM3
SEG34
COM3
—
SE26
SE34
—
SEG25
COM0
SE33
COM0
SEG41
COM0
SEG25
COM1
SEG33
COM1
SEG41
COM1
SEG25
COM2
SEG33
COM2
SEG41
COM2
SEG25
COM3
SEG33
COM3
SEG41
COM3
SE25
SE33
SE41
SEG24
COM0
SEG32
COM0
SEG40
COM0
SEG24
COM1
SEG32
COM1
SEG40
COM1
SEG24
COM2
SEG32
COM2
SEG40
COM2
SEG24
COM3
SEG32
COM3
SEG40
COM3
SE24
SE32
SE40
—
—
xxxx xxxx
xxxx xxxx
---- --xx
xxxx xxxx
xxxx xxxx
---- --xx
xxxx xxxx
xxxx xxxx
---- --xx
xxxx xxxx
xxxx xxxx
---- --xx
0000 0000
0000 0000
---- --00
—
—
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,228
147,229
147,229
147,229
19Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
PIC16F946 only.
© 2007 Microchip Technology Inc.
DS41250F-page 31