ST7PLIT110BF0M3 查看數據表（PDF） - STMicroelectronics

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ST7PLIT110BF0M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40°C to 125°C, unless otherwise specified

Symbol

VIL

VIH

Vhys

Parameter

Input low level voltage 1)

Input high level voltage 1)

Schmitt trigger voltage hysteresis 1)

VOL Output low level voltage 1)2)

RON Pull-up equivalent resistor 3)

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 4)

tg(RSTL)in Filtered glitch duration

Conditions

VDD=5V

IIO=+5mA TA≤85°C

IIO=+2mA TA≤85°C

VDD=5V

VDD=3V 1)

Internal reset sources

Min

Vss - 0.3

0.7xVDD

20

40

20

Typ

2

0.5

0.2

40

70

30

200

Max Unit

0.3xVDD V

VDD + 0.3

V

1.0

V

0.4

80

kΩ

120

μs

μs

ns

Notes:

1. Data based on characterization results, not tested in production.

2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between

VILmax and VDD

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

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