STM32L151CBT6D(2013) 查看數據表（PDF） - STMicroelectronics

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STM32L151CBT6D
(Rev.:2013)

Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

STMicroelectronics 

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

6.3.10

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 39. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class Maximum value(1) Unit

VESD(HBM)

Electrostatic discharge

voltage (human body model)

TA = +25 °C, conforming

to JESD22-A114

2

VESD(CDM)

Electrostatic discharge

voltage (charge device

model)

TA = +25 °C, conforming

to JESD22-C101

II

2000

V

500

1. Based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 40. Electrical sensitivities

Symbol

Parameter

Conditions

LU

Static latch-up class TA = +105 °C conforming to JESD78A

Class

II level A

6.3.11

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDD (for standard pins) should be avoided during normal product operation. However,

in order to give an indication of the robustness of the microcontroller in cases when

abnormal injection accidentally happens, susceptibility tests are performed on a sample

basis during device characterization.

Doc ID 17659 Rev 8

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