STM32L151C8T6TR 查看數據表（PDF） - STMicroelectronics

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STM32L151C8T6TR

Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

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Pin descriptions

STM32L151x6/8/B STM32L152x6/8/B

Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)

Pins

Pins functions

Pin name

Main

function(2)

(after reset)

Alternate functions

Additional

functions

TIM3_CH1/PB4/

90 56 A4 A7 40

PB4

I/O FT NJTRST SPI1_MISO/LCD_SEG8/ COMP2_INP

NJTRST

91 57 C4 C5 41

PB5

I/O FT

PB5

I2C1_SMBA/TIM3_CH2/

SPI1_MOSI/LCD_SEG9

COMP2_INP

92 58 D3 B5 42

PB6

I/O FT

PB6

I2C1_SCL/TIM4_CH1/

USART1_TX

93 59 C3 B4 43

PB7

I/O FT

PB7

I2C1_SDA/TIM4_CH2/

USART1_RX

PVD_IN

94 60 B4 A4 44 BOOT0

IB

BOOT0

-

-

95 61 B3 A3 45

PB8

I/O FT

PB8

TIM4_CH3/I2C1_SCL/

LCD_SEG16/TIM10_CH1

-

96 62 A3 B3 46

PB9

I/O FT

PB9

TIM4_CH4/I2C1_SDA/

LCD_COM3/TIM11_CH1

-

97 - - C3 -

PE0

I/O FT

PE0

TIM4_ETR/LCD_SEG36/

TIM10_CH1

-

98 - - A2 -

PE1

I/O FT

PE1

LCD_SEG37/TIM11_CH1

-

99 63 D4 D3 47

VSS_3

S-

VSS_3

-

-

100 64 E4 C4 48

VDD_3

S-

VDD_3

-

-

1. I = input, O = output, S = supply.

2. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1

and USART1 & USART2, respectively. Refer to Table 2 on page 11.

3. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to VDD.

4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the

LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose

PC14/PC15 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over

the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins

section in the STM32L1xxxx reference manual (RM0038).

5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on (by setting the HSEON bit

in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,

respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off). The HSE has priority over the GPIO

function.

6. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.

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DocID17659 Rev 12

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