PSD4212G6-20UI 查看數據表（PDF） - STMicroelectronics

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PSD4212G6-20UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

Figure 30. Port D Structure

PSD4235G2

DATA OUT

Register

DQ

WR

READ MUX

P

D

B

DIR Register

DQ

WR

DATA OUT

OUTPUT

MUX

DATA IN

OUTPUT

SELECT

CPLD - INPUT

PORT D PIN

Port D – Functionality and Structure

Port D has four I/O pins. See Figure 30. Port D can

be configured to perform one or more of the follow-

ing functions:

s MCU I/O mode

s CPLD Input – direct input to the CPLD, no Input

Macrocells (IMC)

Port D pins can be configured in PSDsoft Ex-

press as input pins for other dedicated func-

tions:

s Address Strobe (ALE/AS, PD0)

s CLKIN (PD1) as input to the Macrocells Flip-

flops and APD counter

s PSD Chip Select Input (CSI, PD2). Driving this

signal High disables the Flash memory, SRAM

and CSIOP.

s Write Enable High-byte (WRH, PD3) input, or as

DBE input from a MC68HC912.

AI04937

Port E – Functionality and Structure

Port E can be configured to perform one or more

of the following functions (see Figure 31):

s MCU I/O Mode

s In-System Programming (ISP) – JTAG port can

be enabled for programming/erase of the PSD

device. (See the section entitled “Reset

(RESET) Timing”, on page 63, for more

information on JTAG programming.)

s Open Drain – pins can be configured in Open

Drain Mode

s Battery Backup features

– PE6 can be configured for a battery input sup-

ply, Voltage Stand-by (VSTBY).

– PE7 can be configured as a Battery-on Indi-

cator (VBATON), indicating when VCC is less

than VBAT.

s Latched Address output – Provide latched

address output.

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