PSD4246G2V-90UI 查看數據表（PDF） - STMicroelectronics
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PSD4246G2V-90UI
STMicroelectronics
PSD4246G2V-90UI Datasheet PDF : 89 Pages
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PSD4235G2
Table 65. Read Timing
Symbol
Parameter
Conditions
-70
Min Max
-90
Min Max
tLVLX
ALE or AS Pulse Width
15
20
tAVLX
Address Setup Time
(Note 3)
4
6
tLXAX
Address Hold Time
(Note 3)
7
8
tAVQV
Address Valid to Data Valid
(Note 3)
70
90
tSLQV
CS Valid to Data Valid
75
100
RD to Data Valid 8-Bit Bus
(Note 5)
24
32
tRLQV
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 2)
31
38
tRHQX RD Data Hold Time
(Note 1)
0
0
tRLRH
RD Pulse Width
(Note 1)
27
32
tRHQZ RD to Data High-Z
(Note 1)
20
25
tEHEL
E Pulse Width
27
32
tTHEH R/W Setup Time to Enable
6
10
tELTL
R/W Hold Time After Enable
0
0
tAVPV
Address Input Valid to
Address Output Delay
(Note 4)
20
25
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
Turbo
Off
Unit
ns
ns
ns
+ 12 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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