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PIC18F46K80T-I/SP 查看數據表(PDF) - Microchip Technology

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PIC18F46K80T-I/SP Datasheet PDF : 623 Pages
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PIC18F66K80 FAMILY
REGISTER 10-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5
R/W-0
IRXIE
R/W-0
WAKIE
R/W-0
ERRIE
R/W-0
TXB2IE
R/W-0
TXB1IE
R/W-0
TXB0IE
R/W-0
RXB1IE
bit 7
R/W-0
RXB0IE/
FIFOFIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRXIE: Invalid Message Received Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 6
WAKIE: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
ERRIE: Error Interrupt Flag bit (multiple sources in the COMSTAT register)
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 4
TXB2IE: Transmit Buffer 2 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3
TXB1IE: Transmit Buffer 1 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 2
TXB0IE: Transmit Buffer 0 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
RXB1IE: Receive Buffer 1 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 0
Bit operation is dependent on the selected mode:
Mode 0:
RXB0IE: Receive Buffer 0 Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
Mode 1:
Unimplemented: Read as ‘0
Mode 2:
FIFOFIE: FIFO Full Interrupt Flag bit
1 = Interrupt is enabled
0 = Interrupt is disabled
2010-2012 Microchip Technology Inc.
DS39977F-page 161

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