PIC18F45K80T-IP 查看數據表（PDF） - Microchip Technology

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PIC18F45K80T-IP

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

16.6 Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and overflows to 0000h. The

Timer3 interrupt, if enabled, is generated on overflow

and is latched in the interrupt flag bit, TMR3IF.

Table 16-3 gives each module’s flag bit.

This interrupt can be enabled or disabled by setting or

clearing the TMR3IE bit. Table 16-3 displays each

module’s enable bit.

16.7 Resetting Timer3 Using the ECCP

Special Event Trigger

If the ECCP modules are configured to use Timer3 and

to generate a Special Event Trigger in Compare mode

(CCP3M<3:0> = 1011), this signal will reset Timer3.

The trigger from ECCP will also start an A/D conversion

if the A/D module is enabled (For more information, see

Section 20.3.4 “Special Event Trigger”.)

The module must be configured as either a timer or

synchronous counter to take advantage of this feature.

When used this way, the CCPR3H:CCPR3L register

pair effectively becomes a Period register for Timer3.

If Timer3 is running in Asynchronous Counter mode,

the Reset operation may not work.

In the event that a write to Timer3 coincides with a

Special Event Trigger from an ECCP module, the write

will take precedence.

Note:

The Special Event Triggers from the

ECCPx module will only clear the TMR3

register’s content, but not set the TMR3IF

interrupt flag bit (PIR2<1>).

Note:

The CCP and ECCP modules use Timers,

1 through 4, for some modes. The assign-

ment of a particular timer to a CCP/ECCP

module is determined by the Timer to CCP

enable bits in the CCPTMRS register. For

more details, see Register 20-2 and

Register 19-2.

TABLE 16-3: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF INT0IF

PIR5

IRXIF

WAKIF

ERRIF

TXB2IF

TXB1IF TXB0IF RXB1IF

PIE5

IRXIE

WAKIE

ERRIE

TX2BIE

TXB1IE TXB0IE RXB1IE

PIR2

OSCFIF

—

—

—

BCLIF

HLVDIF TMR3IF

PIE2

OSCFIE

—

—

—

BCLIE

HLVDIE TMR3IE

TMR3H Timer3 Register High Byte

TMR3L

Timer3 Register Low Byte

T3GCON

TMR3GE T3GPOL

T3GTM

T3GSPM

T3GGO/

T3DONE

T3GVAL

T3GSS1

T3CON

TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16

OSCCON2

—

SOSCRUN

—

SOSCDRV SOSCGO

—

MFIOFS

PMD1

PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

Bit 0

RBIF

RXB0IF

RXB0IE

TMR3GIF

TMR3GIE

T3GSS0

TMR3ON

MFIOSEL

TMR0MD

DS39977F-page 232

 2010-2012 Microchip Technology Inc.

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