ST72T631K4D0 查看數據表（PDF） - STMicroelectronics

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ST72T631K4D0

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

STMicroelectronics 

ST7263

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

7.8.2 I2C - Inter IC Control Interface

I2C/DDC-Bus Timings

Parameter

Standard I2C

Min

Max

Fast I2C

Min

Max

Bus free time between a STOP and START con-

dition

4.7

1.3

Hold time START condition. After this period,

4.0

0.6

the first clock pulse is generated

LOW period of the SCL clock

4.7

1.3

HIGH period of the SCL clock

4.0

0.6

Set-up time for a repeated START condition

4.7

0.6

Data hold time

0 (1)

0 (1)

0.9(2)

Data set-up time

250

100

Rise time of both SDA and SCL signals

1000 20+0.1Cb 300

Fall time of both SDA and SCL signals

300

20+0.1Cb 300

Set-up time for STOP condition

4.0

0.6

Capacitive load for each bus line

400

400

Symbol Unit

TBUF

ms

THD:STA µs

TLOW

µs

THIGH

µs

TSU:STA µs

THD:DAT ns

TSU:DAT ns

TR

ns

TF

ns

TSU:STO ns

Cb

pF

1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL

2) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal

Cb = total capacitance of one bus line in pF

101/109

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