ST72E632K2B0 查看數據表（PDF） - STMicroelectronics

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ST72E632K2B0

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

STMicroelectronics 

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.4 Functional Description

The block diagram of the Serial Control Interface,

is shown in Figure 1. It contains 4 dedicated regis-

ters:

– Two control registers (CR1 & CR2)

– A status register (SR)

– A baud rate register (BRR)

Refer to the register descriptions in Section 0.1.7

for the definitions of each bit.

5.5.4.1 Serial Data Format

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their

own baud rate generator.

Word length may be selected as being either 8 or 9

bits by programming the M bit in the CR1 register

(see Figure 1).

Figure 35. Word Length Programming

9-bit Word length (M bit is set)

Data Frame

Possible

Parity

Bit

Next Data Frame

Next

Start

Bit Bit0

Bit1 Bit2

Bit3

Bit4 Bit5

Bit6

Bit7 Bit8

Stop

Bit

Start

Bit

Start

Idle Frame

Bit

Break Frame

Extra Start

’1’ Bit

8-bit Word length (M bit is reset)

Possible

Next Data Frame

Data Frame

Parity

Bit

Next

Start

Bit Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Stop

Bit

Start

Bit

Start

Idle Frame

Bit

Break Frame

Extra

’1’

Start

Bit

56/109

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