ST72E632K2B0 查看數據表（PDF） - STMicroelectronics

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ST72E632K2B0

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

STMicroelectronics 

ST7263

I²C BUS INTERFACE (Cont’d)

The Acknowledge function may be enabled and

disabled by software.

The I²C interface address and/or general call ad-

dress can be selected by software.

The speed of the I²C interface may be selected be-

tween Standard (0-100 kHz) and Fast I²C (100-

400 kHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

Figure 39. I²C Interface Block Diagram

The SCL frequency (FSCL) is controlled by a pro-

grammable clock divider which depends on the I²C

bus mode.

When the I²C cell is enabled, the SDA and SCL

ports must be configured as floating open-drain

output or floating input. In this case, the value of

the external pull-up resistor used depends on the

application.

When the I²C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

DATA REGISTER (DR)

SDA

SDAI

DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER (OAR)

SCLI

SCL

CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

CONTROL LOGIC

INTERRUPT

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